export PrjDIR=../..
export PrjRTL=${PrjDIR}/design
export PrjSIM=..
export TB_DIR=../testbench

export CODE_BASE_PATH=${PrjRTL}/openc910/C910_RTL_FACTORY

TESTCASE?=hello_world

DUT_FILELIST = -f ${CODE_BASE_PATH}/gen_rtl/filelists/C910_asic_rtl.fl
TB_FILELIST = -f ${TB_DIR}/filelist/smart.fl
TB_FILELIST+= -f ${TB_DIR}/filelist/tb_file.f

all: comp sim

comp:
	vcs -full64 -kdb -sverilog -debug_access+all -debug_region=cell+lib -licqueue \
	-timescale=1ns/1ps -ntb_opts uvm-1.2 +notimingcheck -l vcs_compile.log \
	${DUT_FILELIST} ${TB_FILELIST} -top tb
	@echo "***************************************************"
	@echo "Compile finished."
	@echo "Compile log: vcs_compile.log"
	@echo "***************************************************"

cbuild: ${TESTCASE}_sim_dir
	rm -rf ${TESTCASE}_sim_dir/cbuild; mkdir -p ${TESTCASE}_sim_dir/cbuild
	make -C ${PrjDIR}/firmware/bootrom BUILD_DIR=$(shell pwd)/${TESTCASE}_sim_dir/cbuild TESTCASE=${TESTCASE}
	cp ${TESTCASE}_sim_dir/cbuild/*.pat ${TESTCASE}_sim_dir

sim: ${TESTCASE}_sim_dir cbuild
	cd ${TESTCASE}_sim_dir; ../simv -l sim_${TESTCASE}.log
	@echo "***************************************************"
	@echo "Simulation finished."
	@echo "Simulation log: ${TESTCASE}_sim_dir/sim_${TESTCASE}.log"
	@echo "***************************************************"

${TESTCASE}_sim_dir:
	mkdir -p ${TESTCASE}_sim_dir

regress:
	python3 ../script/regress.py

regress_all:
	python3 ../script/regress.py -cigr runlist 

verdik:
	verdi -elab simv.daidir/kdb.elab++ &

clean:
	rm -rf csrc DVEfiles urgReport simv.vdb simv simv.daidir ucli.key vc_hdrs.h vcs_compile.log 

cleanall: clean
	rm -rf *_sim_dir novas.conf novas.rc verdiLog *.log


